1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a sense amplifier for amplifying a potential difference occurring between a pair of complementary bit lines.
2. Description of Related Art
Semiconductor memory devices such as a dynamic random access memory (DRAM) use sense amplifiers to amplify weak signals read from memory cells. A sense amplifier typically includes a pair of cross-coupled P-channel MOS transistors and a pair of cross-coupled N-channel MOS transistors. The P-channel MOS transistors drive either one of a pair of bit lines to a high level. The N-channel MOS transistors drive the other of the pair of bit lines to a low level (see Japanese Patent Application Laid-Open No. 2004-31908 (Patent Document 1), Japanese Patent Application Laid-Open No. 2004-348896 (Patent Document 2), Japanese Patent Application Laid-Open No. 04-228171 (Patent Document 3), Japanese Patent Application Laid-Open No. 2003-78405 (Patent Document 4), and Japanese Patent Application Laid-Open No. 02-246089 (Patent Document 5)).
In order for sense amplifiers to perform a sensing operation at high speed and with high sensitivity, each pair of cross-coupled transistors (first and second transistors) needs to have exactly matched characteristics. It is also preferred that the P-channel MOS transistors and the N-channel MOS transistors be exactly matched in operation timing.
Patent Documents 1 to 3 describe the layout of transistors that constitute a sense amplifier. The layouts discussed in Patent Documents 1 to 3, however, have had the problem of a reduced sensing margin because a pair of so-called cross-coupled transistors sometimes have a difference in characteristic. For example, two transistors in a pair have different distances from a well edge.
Patent Documents 4 and 5 describe a drive circuit for driving a sense amplifier. The drive circuit discussed in Patent Document 4 simply supplies the high side potential of a bit line to the power supply nodes of a pair of P-channel MOS transistors and the low side potential of a bit line to the power supply nodes of a pair of N-channel MOS transistors. Such a drive circuit has the problem of a slow sensing operation. On the other hand, the drive circuit discussed in Patent Document 5 supplies a potential higher than the high side potential of a bit line to the power supply nodes of a pair of P-channel MOS transistors before supplying the high side potential of a bit line. This can accelerate the sensing speed in the initial stage of the sensing operation.
For the drive circuit discussed in Patent Document 5, however, it is difficult to match the timing of a first control signal PIP which drives the power supply nodes of the pair of P-channel MOS transistors with the timing of a second control signal PIN which drives the power supply nodes of the pair of N-channel MOS transistors. There has thus been the problem of causing a skew in the operation timing. The reason is that the first control signal PIP and the second control signal PIN have different voltages.